This invention relates to a method of evaluating fault coverage, such as testing technology for logic circuits included in a logic LSI, a VLSI, and a large scale circuit formed on a board, in particular, fault simulation technology.
Conventionally, the fault coverage of a test pattern has been evaluated to check how many faults can be detected with use of the test pattern by performing fault simulation on the assumption that arbitrary faults occur in inner nodes of a logic circuit included in a LSI or a large scale circuit formed on a board.
Particularly, according to fault simulation using as an assumed fault a stuck-at fault in which an inner node of a logic LSI is fixed at "0" or "1", the fault can be calculated relatively easily. In addition, it has been known that the fault coverage attained by such fault simulation has strong correlation with a rate of failed devices present among passed devices after performing the device selection by inputting the test pattern into the device and comparing outputs from the device with expected values, and with a failure rate at which failures of the logic LSIs occur in the field after shipping.
Further, when the test pattern has a low fault coverage, the test pattern can be improved to attain excellent fault coverage by manually adding a test pattern which can detect considerable percentage of undetected faults, thereby the shipping quality of the LSIs can be improved.
However, according to the above-mentioned conventional fault simulation method, it takes very long CPU time (e.g. several months) to perform the fault simulation. Due to this problem, the fault simulation has not been always performed for all the developed LSIs except for the case very high quality assurance is essentially required.
In view of the current level and the development of the fault simulation technology and the CPU performance of a work station for executing the fault simulation, this tendency not always to perform the fault simulation seems to remain unchanged in future, if relying merely on developing the current technology.
As an easy solution of the above-mentioned problem, a fault sampling method is employed wherein several to several tens % of faults are sampled to be subjected to the fault simulation. On a suitable condition, the fault coverage evaluation using this fault sampling method can be performed with errors of a few % within a one-order shorter CPU time than that of the fault simulation performed for the 100% assumed fault.
The conventional fault simulator, however, has been intended merely to easily perform the fault simulation of the entire chip. Therefore, when the fault coverage in a new chip including a circuit block once subjected to the fault coverage evaluation is intended to be evaluated, the fault sampling and the fault simulation must be performed again for the new chip including the circuit block.
As mentioned above, the fault simulation resources cannot be effectively used according to the conventional fault sampling method, and the result attained by the former fault simulation cannot be used in the next simulation. This is one of the problems which prevents the spread of the fault sampling method.
In fact, even if the circuit blocks having the same constitution and respectively embedded in LSI nets having different constitutions are subjected to the fault coverage evaluation, there is no possibility of detecting the same fault even by using the same test pattern. There are also present a case where a part of the circuit is not tested due to the deficiency of the embedding technology even if a test pattern is input, and a case where a part of the test pattern is omitted due to some trouble. The cause of the undetection thus cannot be identified easily or surely, and the standardization of the test pattern, which intends to attain a desired level of product quality, has not been attained.
As described above, the conventional fault simulation (in particular, the fault simulation using the fault sampling method) cannot use the best of its advantage, i.e., the reduction of the CPU time required for the fault simulation. In other words, the conventional fault simulation has not satisfied the requirement of the user, which reflects a current trend of the LSI development process: to develop various types of functional blocks and further so many types of derivative LSIs basically by integrating some of these blocks.
As described above, according to the conventional fault simulation based on the sampling technology, the entire portion of the chips must be subjected to the fault sampling and the fault simulation, even if the new chip has a circuit block once subjected to the fault coverage evaluation.
Due to this problem, not only the advantage of the sampling (the reduction of the fault simulation time) cannot be used the best, but also the standardization of test patterns and the effective use of the fault simulation resources cannot be attained.